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  • Küçük Resim Yok
    Öğe
    5G/6G uygulamaları için 65nm CMOS ile 6GHz düşük gürültülü yükselteç tasarımı
    (Institute of Electrical and Electronics Engineers Inc., 2020) Eren, Tamer; Oktay, Zehra Nur; Doğan, Hakan; Savcı, Hüseyin Şerif
    It is envisaged that 6G network technology will be popular due to its higher working frequencies than 5G networks, and this will ensure higher data rates, greater capacity and lower latency. 6G mobile technology will support sub-microsecond delays which makes communication almost instantaneous. Realization of these goals depend on faster circuits with low noise levels in both transmitters and receivers. In this work, a low noise amplifier (LNA) was designed in 65nm UMC CMOS technology with Cadence Spectre. Differential common source topology with integrated inductors were utilized to achieve low differential noise and better matching performance with higher gain. Proposed LNA has 20dB gain at 6GHz, and the gain is higher than 13dB from DC to 8 GHz. Minimum noise figure is 2.24 dB and S11 is -30dB at 6GHz. Simulated IIP3 is -6.5dBm. The design works with 3.6 mA total current from 1.2V supply voltage.
  • Küçük Resim
    Öğe
    A high-resolution time to digital converter design for all digital phase-locked loops
    (İstanbul Medipol Üniversitesi Fen Bilimleri Enstitüsü, 2021) Eren, Tamer; Doğan, Hakan; Aktan, Mustafa
    Phase-locked loops are one of the most significant modules that are used not only for communication circuits but also in other fields like biomedical and computer sciences. There are many types of PLLs such as Analog, Digital, and Software-based ones. However, they have advantages and disadvantages among each other, and All-Digital PLLs have many significant features like programmability and cost efficiency that make them stand out from the rest. Independent from the topology, all PLLs synthesize an output signal whose frequency is proportional to the phase or time difference between input signals. When the alignment between phases is achieved, PLL enters the "locked state". In other words, the frequency of the output signal becomes the same as the input signal. The first step of the phase-locking process is measuring the time distance between incoming signals which are known as Reference and Feedback signals. Different PLL types employ different subblocks to measure phase difference. Due to taking advantages of the digital domain extensively, All-Digital Phase-Locked Loops converts phases of the incoming signals to time and computes the difference between arrival times in terms of known reference. In this thesis, a hybrid time to digital converter with 22.18 ps resolution was designed in 180 nm XFAB technology. The overall working principle was divided into two parts as fine and coarse measurement. Then the top module was verified in Verilog first, and subsequently, behavioral Verilog codes were transformed to gate level ones by RC synthesis. After taking preliminary results in ModelSim, the schematic level of the prototype was synthesized in Cadence Virtuoso software with a pre-designed Standard Cell library. The average current consumption during the error measurement was obtained as 3.9 mA from a 1.8 V supply. After functional and periodic tests, the proposed TDC was tested across corners with ±10% supply voltage variation. Moreover, the same tests were performed for different temperatures from -200 oC to 85 oC degrees. When all tests were completed successfully, the layout of the proposed TDC was done in a 0.057 mm2 area and verified with Mentor Calibre. As the last step, parasitic extraction was performed from layout to observe the effects of parasitics in post-layout simulations.